Performance Modeling for Hardware Thread-Level Speculation

机译：硬件线程级推测的性能建模

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This paper presents a preliminary performance model for hardware Thread-Level Speculation (TLS) in the IBM Blue Gene/Q computer. The model analyzes the TLS behavior and its overhead. We model the scenario when there are 0, 1 and 2 conflicts. The model shows good performance prediction and is verified with experiments. This study helps to understand potential gains from using special purpose TLS hardware to accelerate the performance of codes that, in a strict sense, require serial processing to avoid memory conflicts.

机译：本文介绍了IBM Blue Gene / Q计算机中硬件线程级推测（TLS）的初步性能模型。该模型分析TLS行为及其开销。我们对存在0、1和2个冲突的情况进行建模。该模型显示出良好的性能预测，并通过实验进行了验证。这项研究有助于了解使用特殊用途的TLS硬件来加速可能在严格意义上要求进行串行处理以避免内存冲突的代码的性能的潜在好处。

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《IEEE International Parallel Distributed Processing Symposium》|2014年|1457-1464|共8页
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Ying-Chieh Wang; Che-Rung Lee; Yeh-Ching Chung; I-Hsin Chung; Perrone M.;
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performance evaluation; IBM Blue Gene/Q computer; TLS behavior; TLS hardware; hardware thread-level speculation; memory conflicts; performance prediction; preliminary performance model; serial processing; Analytical models; Computational modeling; Delays; Hardware; Instruction sets; Performance gain; Radiation detectors;

机译：性能评估; IBM Blue Gene / Q计算机; TLS行为; TLS硬件;硬件线程级推测;内存冲突;性能预测;初步性能模型;串行处理;分析模型;计算建模;延迟;硬件;指令集;性能增益;辐射探测器;

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Performance Modeling for Hardware Thread-Level Speculation

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