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Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning

机译：通过自动网表分区和布局规划最大程度地减少了清理工作

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Existing techniques for SEU mitigation on FPGAs by scrubbing do not prevent permanent malfunction of a circuit design in case that the corresponding configuration bits do belong to feedback loops. In this paper, we a) provide a circuit analysis technique to distinguish so-called critical bits from essential bits to determine which parts of a bitstream will need also state-restoring actions after scrubbing and which not. Moreover, b) we will propose floorplanning techniques to reduce the effective number of frames that need to be scrubbed and c), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits may be reduced by up to 48.5% in comparison to a standard approach. For the MTTR calculation, we assume a system with checkpointing using the Xilinx SEM IP core to implement the scrubbing controller.
机译：在相应配置位确实属于反馈环路的情况下，通过擦洗减轻FPGA上SEU的现有技术无法防止电路设计的永久性故障。在本文中，我们（a）提供了一种电路分析技术，可将所谓的关键位与基本位区分开，以确定位流的哪些部分在擦除后还需要状态恢复操作，而哪些则不需要。此外，b）我们将提出布局规划技术以减少需要擦洗的有效帧数; c）实验结果将证明我们的优化方法不仅可以提早发现错误，而且还可以最大程度地减少平均时间电路的修复率（MTTR）。特别是，我们表明，通过使用我们的方法，与标准方法相比，用于数据路径密集型电路的MTTR最多可以降低48.5％。对于MTTR计算，我们假设使用Xilinx SEM IP内核的检查点系统来实现清理控制器。

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