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首页> 外文会议>IEEE International Parallel Distributed Processing Symposium >Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single-Threaded C Programs
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Twill: A Hybrid Microcontroller-FPGA Framework for Parallelizing Single-Threaded C Programs

机译：Twill：用于并行化单线程C程序的混合微控制器-FPGA框架

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摘要

Increasingly System-On-A-Chip platforms which incorporate both microprocessors and re-programmable logic are being utilized across several fields ranging from the automotive industry to network infrastructure. Unfortunately, the development tools accompanying these products leave much to be desired, requiring knowledge of both traditional embedded systems languages like C and hardware description languages like Verilog. We propose to bridge this gap with Twill, a truly automatic hybrid compiler that can take advantage of the parallelism inherent in these platforms. Twill can extract long-running threads from single threaded C code and distribute these threads across the hardware and software domains to more fully utilize the asymmetric characteristics between processors and the embedded reconfigurable logic fabric. We show that Twill provides a significant performance increase on the CHStone benchmarks with an average 1.63 times increase over the pure hardware approach and an increase of 22.2 times on average over the pure software approach while in general decreasing the area required by the reconfigurable logic compared to the pure hardware approach.
机译：越来越多的结合了微处理器和可重编程逻辑的片上系统平台被用于从汽车工业到网络基础设施的多个领域。不幸的是，这些产品附带的开发工具非常不理想，需要了解传统的嵌入式系统语言（如C）和硬件描述语言（如Verilog）。我们建议使用Twill（一种可以自动利用这些平台固有的并行性的真正的自动混合编译器）弥合这种差距。 Twill可以从单线程C代码中提取运行时间较长的线程，并将这些线程分布在硬件和软件域中，以更充分地利用处理器与嵌入式可重新配置逻辑结构之间的非对称特性。我们展示了Twill在CHStone基准上提供了显着的性能提升，与纯硬件方法相比，平均提高了1.63倍，与纯软件方法相比，平均提高了22.2倍，而与之相比，总体上减小了可重新配置逻辑所需的面积纯硬件方法。

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