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Performance analysis of Wallace and radix-4 Booth-Wallace multipliers

机译：Wallace和radix-4 Booth-Wallace乘法器的性能分析

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Multiplication is one of the most commonly used operations in the arithmetic. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. In the previous years the Booth encoding is widely used in the tree multipliers to increase the speed of the multiplier. However, the efficiency of the Booth encoders decreases with the technology scale down. In this paper we showed that the use of Booth encoders in fact increases the delay and power of the Wallace multiplier in the deep submicron technology. The radix-4 Booth-Wallace and the Wallace multipliers are implemented for various sizes and synthesized using Synopsys Design Compiler in 90nm process technology. The synthesis results show that the Wallace multiplier has up to 17% less delay and 70% less power consumption as compared to the radix-4 Booth-Wallace multipliers. The Power-Delay Product (PDP) of the Wallace multiplier is up to 68% lower than the Booth-Wallace multiplier.
机译：乘法是算术中最常用的运算之一。基于华莱士约简树的乘法器为高速乘法提供了一种面积有效的策略。在过去的几年中，Booth编码广泛用于树乘法器中，以提高乘法器的速度。但是，展位编码器的效率会随着技术规模的缩小而降低。在本文中，我们证明了在深亚微米技术中使用Booth编码器实际上会增加Wallace乘法器的延迟和功率。 radix-4 Booth-Wallace和Wallace乘法器可实现各种尺寸，并使用Synopsys Design Compiler以90nm工艺技术进行合成。综合结果表明，与radix-4 Booth-Wallace乘法器相比，Wallace乘法器的延迟降低了17％，功耗降低了70％。华莱士乘法器的功率延迟乘积（PDP）比布斯-华莱士乘法器低68％。

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