According to the problem that multiplier can’t take into account both the path delay and layout area,we proposed a novel structure of 32 bit signed multiplier.Its characteristics are:the multiplier uses the improved Booth encoding to generate a partial product array ranging regularly,and the circuit it brought forth reduces the delay and area compared with traditional method;it employs the improved novel Wallace tree compressing structure which is the combination of 4 -2 compressor and 3 -2 compressor,and to compress 17 partial products into 2 ones only needs 10 XOR-delays,thus speeds up multiplication computation considerably.The whole design was verified on FPGA,and synthesised with SMIC 0.18 μm-based standard unit process.Synthesis results showed that the chip area was 0.1127 mm2 ,and the key path delay was 3.4 ns.Experimental results also showed that the improved multiplier reduced both the key path delay and the layout area.%针对当前乘法器设计难于兼顾路径延时和版图面积的问题，设计一种新型的32位有符号数乘法器结构。其特点是：采用改进的 Booth 编码，生成排列规则的部分积阵列，所产生的电路相比于传统的方法减小了延时与面积；采用由改进的4－2压缩器和3－2压缩器相结合的新型 Wallace 树压缩结构，将17个部分积压缩为2个部分积只需经过10级异或门延时，有效地提高了乘法运算的速度。设计使用 FPGA 开发板进行测试，并采用基于 SMIC 0．18μm 的标准单元工艺进行综合，综合结果显示芯片面积为0．1127 mm2，关键路径延时为3．4 ns。实验结果表明，改进后的乘法器既减少了关键路径延时，又缩小了版图面积。
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