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Fault detection and redundancy design for TSVs in 3D ICs

机译：3D IC中TSV的故障检测和冗余设计

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摘要

Defects in through-silicon vias (TSVs) due to fabrication steps decrease the yield and reliability of 3-D stacked integrated circuits, and hence these defects need to be detected early to reduce chip's DPM. In this paper, a new fault detection and repair method for TSVs in 3D-ICs is proposed. The contribution of the method is to detect stuck-at-faults and delay-based fault in TSV by a scan-based built-in self-test (BIST) architecture. This test architecture supports both pre-bond and post-bond TSV testing. By constructing RC model and analyzing the delay characteristics of TSV, the variation of TSV-to-substrate resistance caused by TSV defects can be mapped to the change of path delay so that the related fault can be detected. Based on the test architecture, we propose a TSV redundancy structure to repair circuit after failed TSVs are detected. Results of fault detection effectiveness are presented through ModelSim simulations using realistic models under 65 nm CMOS technology. And redundancy design leads to 99.9846% recovery rate for TSVs with only 0.2% redundancy rate of TSVs.
机译：由于制造步骤而导致的硅通孔（TSV）缺陷会降低3-D堆叠集成电路的良率和可靠性，因此需要尽早检测这些缺陷以降低芯片的DPM。本文提出了一种3D-ICs中TSV故障检测与修复的新方法。该方法的作用是通过基于扫描的内置自检（BIST）架构来检测TSV中的故障停滞和基于延迟的故障。此测试体系结构支持键合前和键合后TSV测试。通过构建RC模型并分析TSV的延迟特性，可以将TSV缺陷引起的TSV到衬底电阻的变化映射到路径延迟的变化，从而可以检测到相关的故障。基于测试架构，我们提出了一种TSV冗余结构，以在检测到故障TSV之后修复电路。通过使用在65 nm CMOS技术下的实际模型进行的ModelSim仿真，可以提供故障检测有效性的结果。冗余设计可以使TSV的回收率达到99.9846％，而TSV的冗余率仅为0.2％。

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