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Enabling future generation high-speed inspection through a massively parallel e-beam approach

机译：通过大规模并行电子束方法实现下一代高速检测

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New device architectures and materials are being introduced to develop 10 and 7 nm node manufacturing processes. In addition, the increasing complexity of multiple patterning adds significant yield challenges. The critical metrology challenges for yield assurance include defect control, control of critical dimension and critical dimension uniformity, and pattern placement control. To support the industry in meeting those challenges SEMATECH continues to evaluate new disruptive metrology technologies that can meet the requirements for high volume manufacturing (HVM). High-speed massively parallel e-beam defect inspection has the potential to address the key gaps limiting today's patterned defect inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. While SEMATECH targets patterned defect inspection first, the technology also has the potential to support the increasing number of hot spot inspection requirements related to critical dimension uniformity and pattern placement that come with self-aligned quadruple patterning. In addition to wafer applications, next generation mask inspection will benefit from a faster high resolution inspection technology. In late 2014 SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for patterned wafer inspection. The selection of a champion technology was made and a core technology maturation phase started with the goal of enabling the eventual commercialization of an HVM system. This paper begins with a brief overview of the industry need and the program being developed to address it. Key technical topics pertaining to imaging performance and defect sensitivity are then examined. Performance data from early proof of concept systems will be shown. The capabilities in development to accurately access defect sensitivity using the core technology will be discussed, and initial results for two types of samples will be provided. Deve- opment towards the next generation of non-proprietary test samples will also be presented.
机译：正在引入新的器件架构和材料，以开发10和7 nm节点制造工艺。另外，多重图案化的日益复杂增加了显着的成品率挑战。保证产量的关键计量挑战包括缺陷控制，关键尺寸和关键尺寸均匀性的控制以及图案放置控制。为了支持业界应对这些挑战，SEMATECH继续评估可以满足大批量生产（HVM）要求的新型破坏性计量技术。高速大规模并行电子束缺陷检查有可能解决关键缺陷，从而限制当今晶圆厂中的图案化缺陷检查。主要是用于检测超小型关键缺陷的吞吐量和灵敏度。尽管SEMATECH首先以图案缺陷检查为目标，但该技术也有潜力支持越来越多的热点检查要求，这些要求涉及与自对准四重图案形成有关的关键尺寸均匀性和图案放置。除晶圆应用外，下一代掩模检测还将受益于更快的高分辨率检测技术。 2014年底，SEMATECH完成了对用于图形化晶圆检查的多种电子束技术的审查，系统分析和概念验证评估。选择了一项冠军技术，并开始了核心技术成熟阶段，其目标是使HVM系统最终商业化。本文首先简要概述了行业需求以及正在开发的解决方案。然后检查与成像性能和缺陷敏感性有关的关键技术主题。将显示来自概念验证系统的早期性能数据。将讨论使用核心技术精确访问缺陷敏感性的开发能力，并将提供两种类型样本的初始结果。还将介绍面向下一代非专有测试样品的开发。

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