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首页> 外文会议>Annual SEMI Advanced Semiconductor Manufacturing Conference >Inspection challenges for triple patterning at sub-14 nm nodes with broadband plasma inspection platforms
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Inspection challenges for triple patterning at sub-14 nm nodes with broadband plasma inspection platforms

机译：使用宽带等离子体检测平台在14纳米以下节点进行三重图案化的检测挑战

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With the continuous shrink of technology nodes, lithography becomes more and more challenging. At 20 nm node, double patterning technology (DPT) was the usual way of achieving the fine device structures. Until EUV is available as a high volume manufacturing (HVM) solution, DPT or triple patterning technology (TPT) will be required to sustain scaling. However, as the industry goes forward with scaling, for sub-14 nm nodes the chip manufacturers are anticipating three or four masks per layer. Exposing the patterns separately allows the spacing or pitch of the structures to be reduced by a factor of two (or more for triple/quadruple patterning) while increasing the metrology and inspection challenges. As with many of the previous geometry shrinks, there will be the usual concerns about yield and reliability. In order to control and predict yield for sub-14 nm nodes we show that design information when integrated with inspection platforms can help predict design weak spots efficiently. It is the purpose of this paper to elucidate some of the inspection challenges and solutions for sub 14nm device structures.
机译：随着技术节点的不断缩小，光刻技术变得越来越具有挑战性。在20 nm节点处，双图案技术（DPT）是实现精细器件结构的常用方法。在EUV可以用作大批量制造（HVM）解决方案之前，将需要DPT或三重图案技术（TPT）来维持规模。但是，随着行业规模不断扩大，对于14纳米以下的节点，芯片制造商预计每层要使用三个或四个掩模。分开暴露图案可以使结构的间距或间距减小两倍（对于三重/四重图案，则可以减小更多倍），同时增加了计量和检查的难度。与许多以前的几何尺寸缩小一样，通常会有关于成品率和可靠性的担忧。为了控制和预测14纳米以下节点的成品率，我们证明了与检查平台集成时的设计信息可以帮助有效地预测设计薄弱环节。本文的目的是阐明低于14nm器件结构的一些检查挑战和解决方案。

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