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A simple clock-fault detection analog circuit for high-speed crystal oscillators

机译:用于高速晶体振荡器的简单时钟故障检测模拟电路

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This paper presents a simple architecture for clock-fault detection in high-speed applications. The overall principle consists in converting a possible error of time to a logic voltage level. When a high voltage level is present at the output, a reliable clock is detected whereas a low voltage level implies a clock error. This detection system is intended for all System-on-Chip such as microcontrollers which use external clock from 4 MHz to 50 MHz. The proposed circuit is realized in CMOS 40 nm process technology. Simulation results prove the suitability of the structure and its integration on silicon is strongly considered by clock error detection in integrated circuits.
机译:本文提出了一种用于高速应用中的时钟故障检测的简单架构。总体原理在于将可能的时间误差转换为逻辑电压电平。当输出上存在高电压电平时,将检测到可靠的时钟,而低电压电平则表示时钟错误。该检测系统适用于所有片上系统,例如使用4 MHz至50 MHz外部时钟的微控制器。所提出的电路是采用CMOS 40 nm工艺技术实现的。仿真结果证明了该结构的适用性,并通过集成电路中的时钟错误检测强烈考虑了其在硅上的集成。

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