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首页> 外文会议>International Conference on Reliability, Infocom Technologies and Optimization >Novel approach for cache memory simulation at approximately-timed TLM abstraction level for SMP system
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Novel approach for cache memory simulation at approximately-timed TLM abstraction level for SMP system

机译：用于SMP系统的近似定时TLM抽象级别的高速缓存存储器仿真的新方法

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摘要

To meet the ever increasing high speed computing requirements of complex System on Chips (SoC), there has been an increasing trend towards adopting Symmetric Multiprocessing (SMP) Systems encapsulating multiple processing cores each having multi-level cache memory for faster accesses. At an early design phase, estimating the requirement of - cache memory size and levels, prefetching strategy, snooping mechanism and coherency protocol to be adopted may save a lot of RTL simulation time and SoC area. Also, optimized cache parameters facilitate better SoC performance in terms of Bandwidth, latency, FIFO depth, arbitration policies etc. of various IP cores. In this work, keeping above in view, a novel approach is proposed to simulate coherent (Multi-Level) Cache Memory based on MESI protocol for Multi-Core Symmetric Multiprocessing (SMP) System deploying the benefits of Timed TLM simulations at an early design phase. The proposed Cache Memory system is provided with the memory reference traces extracted from earlier SoC simulation. Based on the user requirement, a memory hierarchy is dynamically generated which produces various cache memory access statistics which can be appropriately used for optimizing Cache Memory parameters.
机译：为了满足复杂的片上系统（SoC）不断增长的高速计算要求，采用对称多处理（SMP）系统的趋势日益增长，该系统封装了多个处理内核，每个处理内核都具有多层高速缓存以实现更快的访问。在早期设计阶段，估计要采用的缓存存储器大小和级别，预取策略，侦听机制和一致性协议的要求可以节省大量RTL仿真时间和SoC面积。同样，优化的高速缓存参数可在各种IP内核的带宽，延迟，FIFO深度，仲裁策略等方面促进更好的SoC性能。在上面的工作中，提出了一种新颖的方法，该方法基于MESI协议来仿真多核对称多处理（SMP）系统的相干（多级）高速缓存，在设计的早期阶段就利用了定时TLM仿真的优势。拟议的高速缓存系统具有从早期SoC仿真中提取的存储器参考轨迹。根据用户需求，动态生成内存层次结构，该层次结构会生成各种缓存访问统计信息，这些统计信息可用于优化缓存参数。

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