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A novel ultra high speed and configurable discrete wavelet packet transform architecture

机译：一种新颖的超高速可配置离散小波包变换架构

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This work is dedicated to present a new architecture of Discrete Wavelet Packet Transform (DWPT) implemented in FPGA using a parallel direct FIR () filter. The main target of our architecture is to provide an effective performance trade-off, where it significantly increases the throughput with a restricted amount of hardware. It is smartly connect based on low-pass and high-pass filters in the Mallat-tree algorithm by a clever sharing of the hardware resources. This architecture is fully configurable in synthesis according to parallel degree, the tree depth (number of tree levels), the order of the filters and the filter quantization coefficient. Consequently, the simulation results accelerated to an approximate value of P*(Frequency). Furthermore, the tree depth and filters order has little impact (only due to place and route variations) on throughput. This architecture was synthesized using Altera Quartus prime lite edition targeting an Altera Cyclone IV - (FPGA) and it was developed in VHDL at RTL level modeling.
机译：这项工作致力于介绍使用并行直接FIR（）滤波器在FPGA中实现的离散小波包变换（DWPT）的新架构。我们架构的主要目标是提供有效的性能折衷，在有限的硬件数量下显着提高吞吐量。通过巧妙共享硬件资源，可基于Mallat树算法中的低通和高通滤波器进行智能连接。根据并行度，树深度（树级别数），滤波器的阶数和滤波器量化系数，可以在合成中完全配置此体系结构。结果，模拟结果加速到近似值P *（频率）。此外，树的深度和过滤器的顺序对吞吐量几乎没有影响（仅由于位置和路线的变化）。该架构是使用针对Altera Cyclone IV-（FPGA）的Altera Quartus prime lite版本综合而成的，并在VHDL中以RTL级别建模进行开发。

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