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首页> 外文会议>International Conference on Microelectronics >Full implementation of a capacitance-to-digital converter system based on SAR logic and charge redistribution technique
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Full implementation of a capacitance-to-digital converter system based on SAR logic and charge redistribution technique

机译：完全实现基于SAR逻辑和电荷再分配技术的电容数字转换器系统

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This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the transistor level. The system, which is fully automated with a universal clock signal, is tested for real time Cadence simulations using a 130nm model from which static and dynamic parameters are extracted. The average static and dynamic current consumption becomes in the order of 200μA using a 1.2V power supply. The tested specifications are compared with a similar CDC implementation and proved an overall enhancement and superiority on both power consumption and conversion rate performance metrics.
机译：本文演示了一种基于电荷重新分配技术和以370 kHz采样率运行的逐次逼近寄存器（SAR）逻辑的低功耗6位单端基于电压的电容数字转换器（CDC）电路。引入了与低功耗比较器集成的SAR逻辑控制单元的拟议实现，其中系统模块完全构建在晶体管级。该系统使用通用时钟信号实现了全自动，并使用130nm模型测试了实时Cadence仿真，并从中提取了静态和动态参数。使用1.2V电源时，平均静态和动态电流消耗约为200μA。将经过测试的规范与类似的CDC实施方案进行了比较，并证明了在功耗和转换率性能指标上的总体增强和优越性。

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