• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>International Conference on Microelectronics >Full implementation of a capacitance-to-digital converter system based on SAR logic and charge redistribution technique
【24h】

Full implementation of a capacitance-to-digital converter system based on SAR logic and charge redistribution technique

机译：基于SAR逻辑和电荷再分配技术的电容到数字转换器系统的全面实现

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the transistor level. The system, which is fully automated with a universal clock signal, is tested for real time Cadence simulations using a 130nm model from which static and dynamic parameters are extracted. The average static and dynamic current consumption becomes in the order of 200μA using a 1.2V power supply. The tested specifications are compared with a similar CDC implementation and proved an overall enhancement and superiority on both power consumption and conversion rate performance metrics.
机译：本文演示了基于低功率6位单端电容的电容到数字转换器（CDC）电路，基于充电再分布技术和以370kHz采样率运行的连续近似寄存器（SAR）逻辑。介绍了与低功率比较器集成的SAR逻辑控制单元的建议实现，其中系统块完全基于晶体管电平。使用通用时钟信号完全自动化的系统用于使用130nm模型来测试实时Cadence模拟，从中提取静态和动态参数。使用1.2V电源，平均静态和动态电流消耗量为200μA的顺序。测试规范与类似的CDC实施进行了比较，并证明了对功耗和转换率绩效指标的总体增强和优越性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号