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首页> 外文会议>IEEE International System-on-Chip Conference >A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs
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A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs

机译：用于定时误差弹性系统设计的低扇区，低功耗和低泄漏错误检测闩锁

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摘要

The error-detecting latch (EDL), which consists of a latch and a transition detector (TD), is the key circuit to the success of timing-error resilient system design. In order to realize a truly variation-resilient design, it is imperative for the EDL to have low overheads in area, power, and leakage while maintaining robustness across all process/voltage/temperature (PVT) corners. This paper proposes a new EDL that achieves the lowest layout area and lowest active and leakage power consumption compared to all previous EDLs. The excellent features are due to a new TD, which requires a small number of transistors and whose logic style allows minimum transistor sizing even in the event of serious PVT variations. Post-layout simulations for various EDL designs in 28-nm CMOS show that the proposed EDL is 26% smaller in area, and achieves 4% and 33% reduction in active and leakage power consumption, respectively, in comparison to the state-of-the-art EDL. The proposed EDL also shows the best voltage scalability in achieving higher power and leakage reduction when operating at the minimum supply voltage (Vmin).
机译：由锁存器和转换检测器（TD）组成的错误检测锁存器（EDL）是定时误差弹性系统设计成功的关键电路。为了实现真正的变化弹性设计，EDL必须在面积，电源和泄漏中具有低开销，同时在所有处理/电压/温度（PVT）角上保持鲁棒性。本文提出了一种新的EDL，与所有先前的EDL相比，实现了最低的布局区域和最低的主动和漏电功耗。优异的功能是由于新的TD，这需要少量晶体管，并且其逻辑风格即使在发生严重PVT变化的情况下也允许最小晶体管尺寸。 28-NM CMOS中各种EDL设计的后布局模拟表明，建议的EDL在面积上较小26％，并且与状态相比，达到了4％和漏电功耗降低了4％和33％艺术EDL。所提出的EDL还示出了在最小电源电压（VMIN）上运行时实现更高功率和泄漏减少的最佳电压可扩展性。

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