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首页> 外文会议>IEEE International System-on-Chip Conference >A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs
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A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs

机译：用于时序误差弹性系统设计的低面积，低功耗和低泄漏误差检测锁存器

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摘要

The error-detecting latch (EDL), which consists of a latch and a transition detector (TD), is the key circuit to the success of timing-error resilient system design. In order to realize a truly variation-resilient design, it is imperative for the EDL to have low overheads in area, power, and leakage while maintaining robustness across all process/voltage/temperature (PVT) corners. This paper proposes a new EDL that achieves the lowest layout area and lowest active and leakage power consumption compared to all previous EDLs. The excellent features are due to a new TD, which requires a small number of transistors and whose logic style allows minimum transistor sizing even in the event of serious PVT variations. Post-layout simulations for various EDL designs in 28-nm CMOS show that the proposed EDL is 26% smaller in area, and achieves 4% and 33% reduction in active and leakage power consumption, respectively, in comparison to the state-of-the-art EDL. The proposed EDL also shows the best voltage scalability in achieving higher power and leakage reduction when operating at the minimum supply voltage (Vmin).
机译：由锁存器和转换检测器（TD）组成的检错锁存器（EDL）是成功实现定时误差弹性系统设计的关键电路。为了实现真正的抗变化设计，EDL必须在面积，功耗和泄漏方面具有较低的开销，同时在所有过程/电压/温度（PVT）角上保持鲁棒性。本文提出了一种新的EDL，与所有以前的EDL相比，它具有最低的布局面积以及最低的有源和泄漏功耗。出色的功能归功于新的TD，它需要少量的晶体管，并且即使在严重的PVT变化的情况下，其逻辑样式也可以使晶体管的尺寸最小化。在28nm CMOS中对各种EDL设计进行布局后仿真，结果表明，与未开发状态相比，拟议的EDL面积减小了26％，有效功耗和泄漏功耗分别降低了4％和33％。最新的EDL。当以最小电源电压（Vmin）工作时，建议的EDL还显示出最佳的电压可扩展性，以实现更高的功率和更低的泄漏。

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