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首页> 外文会议>IEEE International System-on-Chip Conference >Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits
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Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits

机译：朝向设计优化的低功耗可逆多路分解器，用于新兴纳米电路

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摘要

Reversible Logic plays a vital role in the field of nanotechnology and quantum computing. One of the most challenging issues in circuit design is power consumption. Reversible logic is one of the ways to optimize power consumption. This paper presents an efficient approach for designing optimized reversible demultiplexer which consumes less power. A generalized approach is proposed to design 1-to -n reversible demultiplexer. Theorem on the numbers of gates, garbage outputs and quantum cost has been presented. The comparative results show that the proposed design is much better than the existing designs in terms of garbage outputs, gate counts and quantum cost. The proposed reversible demultiplexer also requires less power and less area than existing demultiplexers. The proposed design is simulated in DSCH 3.5 software which verifies the correctness of the proposed circuit.
机译：可逆逻辑在纳米技术和量子计算领域起着至关重要的作用。电路设计中最具挑战性的问题之一是功耗。可逆逻辑是优化功耗的方法之一。本文介绍了设计优化可逆多路分解器的有效方法，该多路分解器消耗更少的功率。提出了一种广义方法来设计1-NN可逆的解复用器。介绍了大门，垃圾输出和量子成本的定理。比较结果表明，所提出的设计比垃圾输出，栅极计数和量子成本的现有设计要好得多。所提出的可逆多路分解器还需要比现有的多路分解器更少的功率和更少的区域。所提出的设计在DSCH 3.5软件中模拟，验证所提出的电路的正确性。

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