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A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique

机译：一种具有模式识别能力和间隔压缩技术的内容适应的FPGA内存架构

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Modern high-energy physics experiments such as the Compact Muon Solenoid experiment at CERN produce an extraordinary amount of data every 25ns. To handle a data rate of more than 50Tbit/s a multi-level trigger system is required, which reduces the data rate. Due to the increased luminosity after the Phase-II-Upgrade of the LHC, the CMS tracking system has to be redesigned. The current trigger system is unable to handle the resulting amount of data after this upgrade. Because of the latency of a few microseconds the Level 1 Track Trigger has to be implemented in hardware. State-of-the-art pattern recognition filter the incoming data by template matching on ASICs with a content addressable memory architecture. A first implementation on an FPGA, which replaces the content addressable memory of the ASIC, has been developed. This design combines the advantages of a content addressable memory and an efficient utilization of the logics elements of an FPGA. This paper presents an extension of this FPGA design, which is based on the idea of data compression and assemble the stored data to appropriate packages and drastically reduces the required number of write and read cycles. Furthermore, the extended design meets the strong timing constraints, possesses the required properties of the content addressable memory and enabled a compressed storage of an increased amount of data.
机译：现代高能量物理实验，如Cern Cern Codal Muon螺线管实验每25ns产生非凡的数据量。要处理超过50Tbit / s的数据速率，需要多级触发系统，这降低了数据速率。由于LHC升级后的亮度增加，必须重新设计CMS跟踪系统。当前触发系统无法在此升级后处理产生的数据量。由于几微秒的延迟，级别1轨道触发器必须以硬件实现。最先进的模式识别通过模板匹配在ASIC上与内容可寻址内存架构进行匹配过滤传入数据。已经开发了FPGA上的第一个实现，该FPGA替换了ASIC的内容可寻址存储器。该设计结合了内容可寻址存储器的优点，以及FPGA的逻辑元件的有效利用。本文介绍了此FPGA设计的扩展，该设计基于数据压缩和将存储的数据组装到适当的包，并大大减少了所需的写入数和读取周期。此外，扩展设计符合强度的时序约束，具有内容可寻址存储器的所需特性，并使能增加的数据量的压缩存储。

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