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首页> 外文会议>IEEE International System-on-Chip Conference >Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing
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Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing

机译：并行计算中的屏障同步的广播和动力感知无线NOC

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摘要

Efficient synchronization is one of the basic requirements of effective parallel computing. A key operation of the POSIX Thread standard (PThread) is barrier synchronization, where multiple threads block on a user-specified point of execution until all of them have reached it. Conventional architectures for broadcast operations limit the achievable performance benefits as synchronization is significantly affected due to critical path communications. This increases the network latency and degrades the performance dramatically. A Wireless Network-on-Chip (WiNoC) offers a promising solution to reduce the long distance/critical path communication bottlenecks of conventional architectures by augmenting them with single hop, long-range wireless links. In this paper, we propose a power-aware broadcast enabled WiNoC architecture to reduce the cost of broadcast operations for barrier-based applications. The proposed architecture reduces the barrier synchronization cost up to 43.97% regarding network latency under the PARSEC benchmarks. It also saves up to 80.49% idle-state power consumption in WIs for a 64-core system compared with the conventional WiNoC architecture without incurring significant overhead.
机译：高效同步是有效并行计算的基本要求之一。 POSIX线程标准（PTHREAD）的关键操作是屏障同步，其中多个线程在用户指定的执行点上块，直到它们都已达到它。广播操作的传统架构限制了可实现的性能益处，因为关键路径通信由于同步受到显着影响。这增加了网络延迟并急剧降低了性能。无线网络（WinoC）提供了一个有希望的解决方案，可以通过使用单跳，远程无线链路增强传统架构的长距离/关键路径通信瓶颈。在本文中，我们提出了一种动力感知的广播，使能WinoC架构，以降低基于障碍的应用程序的广播操作的成本。拟议的架构在Parsec基准下的网络延迟下降至43.97％的阻挡同步成本。与传统的WinoC架构相比，它还可以节省高达80.49％的WIS为64核系统的闲置功耗，而无需导致显着的开销。

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