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A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks

机译：深神经网络多基对数计算的低功耗算术元件

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摘要

Computational complexity and memory intensity are crucial in deep convolutional neural network algorithms for deployment to embedded systems. Recent advances in logarithmic quantization has manifested great potential in reducing the inference cost of neural network models. However, current base-2 logarithmic quantization suffers from performance upper limit and there is few work that studies hardware implementation of other bases. This paper presents a multi-base logarithmic scheme for Deep Neural Networks (DNNs). The performance of Alexnet is studied with respects to different quantization resolutions. Base √2 logarithmic quantization is able to raise the ceiling of top-5 classifying accuracy from 69.3% to 75.5% at 5-bit resolution. A segmented logarithmic quantization method that combines both base-2 and base √2 is then proposed to improve the network top-5 accuracy to 72.3% in 4-bit resolution. The corresponding arithmetic element hardware has been designed, which supports base √2 logarithmic quantization and segmented logarithmic quantization respectively. Evaluated in UMC 65nm process, the proposed arithmetic element operating at 500MHz and 1.2V consumes as low as 120 μW. Compared with 16-bit fixed point multiplier, our design achieves 58.03% smaller in area, with 73.74% energy reduction.
机译：计算复杂性和内存强度都深陷卷积神经网络算法部署到嵌入式系统是至关重要的。在对数量化的最新进展在减少神经网络模型的推断成本体现了巨大的潜力。然而，从性能电流上限2为底的对数量化患有且有少数的工作，研究硬件实现的其他基地。本文提出了深神经网络（DNNs）的多基对数方案。 Alexnet的性能进行了研究与尊重不同的量化分辨率。基地√2对数量是能够以5位分辨率从69.3％提高前五名分类准确性的上限75.5％。分段，结合两个基-2和碱对数量化法√2然后提出了改进网络顶部-5精度72.3％在4位的分辨率。对应的运算元件的硬件已经被设计，√2对数量化和分段对数量化分别支撑基座。在UMC 65nm工艺评估，所提出的运算元件在500MHz操作和1.2V消耗低至120μW。与16位定点乘法器相比，我们的设计实现了面积58.03％，与节能减排73.74％。

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