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首页> 外文会议>IEEE International System-on-Chip Conference >A 0.4V 320Mb/s 28.7μW 1024-bit configurable multiplier for subthreshold SOC encryption
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A 0.4V 320Mb/s 28.7μW 1024-bit configurable multiplier for subthreshold SOC encryption

机译：用于亚阈值SOC加密的0.4V 320MB / s28.7μW1024位可配置乘法器

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摘要

A folding multiplier tailored to subthreshold operation is presented for ultra-low-power en/decryption in SOC. The multiplier is composed of radix-4 booth encoder and two 544×16 bit partial product reduction tree arrays and reconfigurable data paths. The folding architecture can be configured for multiple multiplications with different bit size. Novel 6-2 compressors are applied to the reduction tree with 4-2 compressors. The tree can compresses 16 bit products and carryins into 1 bit sum and carry within the delay of 7 XOR gates. Innovatively, a novel custom ratioed logic style is adopted in critical logic paths to fundamentally speed up the subthreshold operation. Fabricated in 90 nm CMOS, the proposed design indicates competent subthreshold operation. It can operate at 0.4V supply or below with power consumption of 28.7 μW and throughput of 320 Mb/s.
机译：为SoC中的超低功耗ZH /解密提供给亚阈值操作的折叠乘法器。乘法器由RADIX-4展位编码器和两个544×16位部分产品还原树阵列组成和可重新配置的数据路径。可以配置折叠架构，用于多个具有不同位大小的乘法。新颖的6-2压缩机用4-2压缩机施加到减速树上。树可以将16位产品压缩成1位总和，并携带在7个XOR门的延迟内。创新性地，在关键逻辑路径中采用了一种新颖的自定义比率逻辑样式，从而从根本上加速亚阈值操作。所提出的设计，在90 nm CMOS中制造，表明称职的亚阈值操作。它可以以0.4V电源或低于28.7μW的功耗和320 MB / s的吞吐量操作。

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