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A comparator timing assisted SAR ADC technique with reduced conversion cycles

机译：比较器时序辅助SAR ADC技术，转换周期降低

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摘要

This paper presents a technique that utilizes comparator timing information to accelerate successive approximation register (SAR) analog-to-digital converter (ADC) conversion process. With the scaling down of power supply voltage, the comparator delay is exponentially increasing. Thus, more information can be potentially extracted from the comparator transient response. In the proposed approach, the comparator delay is compared with multiple timing reference levels. Based on such timing information as well as the comparator logic output, the search space can be more quickly refined compared to the conventional SAR ADC scheme that only relies on the comparator logic output. The paper also investigates how to optimally select such timing reference levels while considering their associated uncertainties. To demonstrate its effectiveness, the proposed technique is used in the design of a 0.5 V 10-bit SAR ADC with four auxiliary levels. Simulations show that the maximum number of conversion cycles of the ADC is 6 and in average it only takes 5.04 conversion cycles to complete the conversion process.
机译：本文介绍了一种利用比较器时序信息来加速连续近似寄存器（SAR）模数转换器（ADC）转换过程的技术。随着电源电压的缩放，比较器延迟是指数增长的。因此，可以从比较器瞬态响应可能提取更多信息。在所提出的方法中，将比较器延迟与多个定时参考水平进行比较。基于此类时序信息以及比较器逻辑输出，与传统的SAR ADC方案相比，搜索空间可以更快地改进，该方案仅依赖于比较器逻辑输出。本文还调查如何在考虑相关的不确定性时最佳地选择此类时序参考水平。为了展示其有效性，所提出的技术用于设计0.5V 10位SAR ADC，具有四个辅助水平。模拟表明，ADC的最大转换周期数为6，平均仅需要5.04转换周期以完成转换过程。

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