• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>IEEE International System-on-Chip Conference >Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application
【24h】

Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application

机译：面积高效的11位混合双VDD ADC，具有自校准的神经传感应用

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented a low voltage area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. To reduce the total amount of capacitance, the proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined based ADC and successive approximation register (SAR) ADC. The three most significant bits are detected by a modified vernier structure delay-line-based ADC. Self-timed power management including dual voltage supply, power-gating and multi-threshold CMOS are employed and the capacitance mismatch due to process variation is compensated using a self-calibration scheme. The proposed 11 bit ADC is implemented in TSMC 90nm general propose (GP) CMOS technology. Post-sim results indicate that ENOB of 9.71-bits at 32KS/s sampling rate can be achieved with only 982nW power consumption and 0.026-mm2. The FOM of the proposed hybrid ADC is 36.75fJ/conversion-step.
机译：小型化神经传感微系统对脑功能调查越来越重要。本文提出了一种低压面积功率高效的11位混合模数转换器（ADC），具有用于神经传感应用的自校准。为了减少电容的总量，所提出的混合ADC由3位粗调和8位微调与基于延迟衬里的ADC和连续近似寄存器（SAR）ADC组成。由修改的Vernier结构延迟线的ADC检测到三种最高的比特。采用包括双电压供应，电力选通和多阈值CMOS的自定时电源管理，并且使用自校准方案补偿引起的处理变化引起的电容不匹配。所提出的11位ADC在TSMC 90nm将军（GP）CMOS技术中实施。后SIM后结果表明，只有982NW功耗和0.026-mm2，只能实现9.71位的9.71位的eNOB。所提出的混合ADC的FOM为36.75FJ /转换步骤。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号