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An ultra-low power voltage-to-time converter (VTC) circuit for low power and low speed applications

机译：用于低功耗和低速应用的超低功率电压 - 时转换器（VTC）电路

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摘要

An ultra-low power voltage-to-time converter (VTC) circuit is proposed. The VTC circuit is compatible with wide range of applications (i.e. sensors, integrated DC-DC voltage converters) especially for time-based analog-to-digital converters (T-ADCs). In T-ADCs, the input voltage signal is first converted into a delay pulse using the VTC circuit, then this delay signal is converted into a digital code through time-to-digital converter (TDC). The main advantages of the T-ADC are that it: 1) eliminates the need for pre-amplifier stages, 2) operates at low supply voltage, and 3) supports low-speed applications as well as high-speed applications. In this paper, two VTC architectures are presented: a single ended architecture, and a fully differential architecture. The core VTC architecture uses a modified current starved inverter biased in subthreshold to maintain low-power consumption level. A prototype of the proposed VTC is implemented in 130nm CMOS technology, it exhibits a nonlinearity of 1 % per 150-mV for single-ended architecture, while exhibits nonlinearity of ±0.4 % per 240-mV for the fully differential one.
机译：提出了超低功率电压与时转换器（VTC）电路。 VTC电路与各种应用（即传感器，集成的DC-DC电压转换器）兼容，尤其是基于时间的模数转换器（T-ADC）。在T-ADC中，首先使用VTC电路将输入电压信号转换成延迟脉冲，然后通过时间到数字转换器（TDC）将该延迟信号转换为数字代码。 T-ADC的主要优点是：1）消除了对预放大器级的需要，2）在低电源电压下操作，3）支撑低速应用以及高速应用。在本文中，提出了两个VTC架构：单一结束的架构和完全差分架构。核心VTC架构采用修改的电流饥饿逆变器偏向于亚阈值以保持低功耗级别。所提出的VTC的原型是在130nm的CMOS技术中实现的，它表现出每150 mV的非线性，用于单端架构，虽然完全差动的架构为每240 mV的非线性为±0.4％。

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