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首页> 外文期刊>電子情報通信学会技術研究報告. シリコン材料·デバイス. Silicon Devices and Materials >Dynamically controllable DC level converter (DCLC) technique to reduce power dissipation, and application to high-speed, low-power circuits
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Dynamically controllable DC level converter (DCLC) technique to reduce power dissipation, and application to high-speed, low-power circuits

机译：动态可控直流电平转换器（DCLC）技术可减少功耗，并应用于高速，低功率电路

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New dynamically Controllable DC voltage Level Converter (DCLC) technique has been developed for use in high-speed, low-power circuits. The level converter can increase the DC voltage which is supplied to a active-load circuit on request, or supply a minimal DC voltage to a load circuit in the stand-by mode so that sub-threshold currents can be reduced. Ripple carry adders (RCAs) and SRAMs were designed using 0.13-μm CMOS technology to examine the effectiveness of DCLCs in power reduction. SPICE simulation results showed that the power dissipation P{sub}(ST) at the stand-by mode for an 8-bit RCA at a clock frequency of 100 MHz with on-chip DCLCs was 1.03 nW, a reduction to 4.54% of that of an equivalent 8-bit RCA. The active power P{sub}(AT) of the 8-bit RCA with on-chip DCLCs was 63.9μW, a reduction to 65.6% of that of the conventional 8-bit RCA, while the output signal delay was 0.79 nsec that was only 3.8% longer than that of the conventional 8-bit RCA. P{sub}(ST) of a 512-bit SRAM with on-chip DCLCs was 1.04μW, 29.1% of the value for an equivalent conventional SRAM, with the read-access time of 286 psec, only 1.06% longer than that (283 psec) of a conventional 512-bit SRAM.
机译：已经开发出了新的动态可控直流电压电平转换器（DCLC）技术，用于高速，低功率电路。电平转换器可以根据需要增加提供给有功负载电路的DC电压，或者在待机模式下向负载电路提供最小的DC电压，从而可以降低亚阈值电流。纹波进位加法器（RCA）和SRAM是使用0.13μmCMOS技术设计的，旨在检验DCLC在降低功耗方面的有效性。 SPICE仿真结果表明，采用片上DCLC时，时钟频率为100 MHz的8位RCA在待机模式下的功耗P {sub}（ST）为1.03 nW，降低了4.54％等效的8位RCA。带有片上DCLC的8位RCA的有功功率P {sub}（AT）为63.9μW，比传统的8位RCA降低了65.6％，而输出信号延迟为0.79 ns。仅比传统的8位RCA长3.8％。带有片上DCLC的512位SRAM的P {sub}（ST）为1.04μW，是同等传统SRAM的29.1％，读取访问时间为286psec，仅比其长1.06％（传统的512位SRAM（283 ps）。

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