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Digital LDO modeling for early design space exploration

机译：早期设计空间探索的数字LDO模型

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Digital low dropout (LDO) voltage regulators have been widely used in the latest low-power circuits that involve fine-grain power management. Due to the mixture of discrete- and continuous-time operation as well as the nonlinear comparator gain, it is difficult to derive the closed-loop transfer function for a digital LDO. The use of its open-loop transfer function is also limited due to the non-constant feedback factor. Thus, it is not easy to predict digital LDO performance in the early design stage, which limits designer's capability to effectively explore the design space. This paper presents closed-form expressions for estimating critical performance parameters of digital LDO circuits, such as settling time and peak control error. The accuracy of the predictions is validated by comparing with circuit simulation results. The derived formulas can be used by designers or integrated into design automation tools.
机译：数字低压差（LDO）电压稳压器已广泛应用于最新的低功耗电路，涉及细晶电源管理。由于离散和连续时间操作的混合以及非线性比较器增益，难以导出数字LDO的闭环传递函数。由于非恒定反馈因子，其开环传递函数的使用也受到限制。因此，在早期设计阶段预测数字LDO性能并不容易，这限制了设计者能够有效地探索设计空间的能力。本文介绍了用于估计数字LDO电路的关键性能参数的闭合表达式，例如建立时间和峰值控制误差。通过与电路仿真结果进行比较，验证了预测的准确性。衍生的公式可以由设计者使用或集成到设计自动化工具中。

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