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Novel lightweight FF-APUF design for FPGA

机译：FPGA的小说轻量级FF-APUF设计

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Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. The proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. The proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66% in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40% on FPGA, which significantly improves upon a uniqueness of 9% achieved in previous work.
机译：物理不可渗透功能（PUF）是一种新型的物理安全原语，其能够从设备中提取数字标识符，例如现场可编程门阵列（FPGA）或应用特定集成电路（ASIC）。由于它们的灵活性和更低的市场时间，FPGA越来越多地用于许多应用程序。仲裁器PUFS（APUFS）是最广泛研究的PUF设计之一。然而，它们经常遭受卓越的唯一性和可靠性特性，难以在FPGA中实现并且消耗过度的FPGA资源。为了解决这些问题，提出了一种新的FF-FF-APUF）设计，提供紧凑的架构，结合强烈的独特性和良好的可靠性。它专为FPGA而设计。基于最新28 NM技术Xilinx Artix-7 FPGA，在低成本的NEXYS4董事会上验证了拟议的工作。所提出的FF-APUF电路用于产生1位响应的电路仅消耗44个切片，这在先前的相关研究中的硬件资源中节省了超过66％。此外，实验结果表明唯一性和可靠性的改善。特别地，响应位的预期唯一性在FPGA上为40％，这显着提高了以前的工作中实现的9％的唯一性。

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