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首页> 外文会议>International symposium on multispectral image processing and pattern recognition >Hardware-efficient implementation of digital FIR filter using fast first-order moment algorithm
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Hardware-efficient implementation of digital FIR filter using fast first-order moment algorithm

机译：使用快速一阶矩算法在硬件上实现数字FIR滤波器

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As the digital finite impulse response (FIR) filter can be transformed into the shift-add form of multiple small-sized first-order moments, based on the existing fast first-order moment algorithm, this paper presents a novel multiplier-less structure to calculate any number of sequential filtering results in parallel. The theoretical analysis on its hardware and time-complexities reveals that by appropriately setting the degree of parallelism and the decomposition factor of a fixed word width, the proposed structure may achieve better area-time efficiency than the existing two-dimensional (2-D) memoryless-based filter. To evaluate the performance concretely, the proposed designs for different taps along with the existing 2-D memoryless-based filters, are synthesized by Synopsys Design Compiler with 0.18-μm SMIC library. The comparisons show that the proposed design has less area-time complexity and power consumption when the number of filter taps is larger than 48.
机译：由于数字有限冲激响应（FIR）滤波器可以转换为多个小型一阶矩的移位加法形式，因此，在现有快速一阶矩算法的基础上，本文提出了一种新颖的无乘法器结构。并行计算任意数量的顺序过滤结果。关于其硬件和时间复杂性的理论分析表明，通过适当设置并行度和固定字宽的分解因子，与现有的二维（2-D）相比，所提出的结构可以实现更好的时域效率。基于无内存的过滤器。为了具体评估性能，由Synopsys Design Compiler使用0.18μm的SMIC库综合了针对不同抽头的建议设计以及现有的基于2D无记忆的滤波器。比较表明，当滤波器抽头的数量大于48时，所提出的设计具有较小的区域时间复杂度和功耗。

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