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1GigaRad TID impact on 28nm HEP analog circuits

机译：1GigaRad TID对28nm HEP模拟电路的影响

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The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.
机译：CERN大型强子对撞机（High Luminosity LHC）未来升级后，预计总电离剂量（TID）水平将严重影响电子设备的性能。在运行10年后，TID级别为1GigaRad会累积在像素检测器的最内层，这可能会损坏读出电路的性能，并在实验中造成重大故障。为了避免这种情况，为读出ASIC选择合适的技术是关键。本文介绍了在1 GigaRad TID照射下，均采用TSMC 28nm体CMOS技术实现的单个晶体管和模拟电路的特性。与pMOS相比，nMOS器件的电阻更高，这表明电参数的衰减很小。然而，相当大的泄漏电流增量是不可忽略的，因为它可能会影响模拟电路，如本文所述。在拟议的模拟电路中，高辐射水平会导致电荷敏感型前置放大器的时间响应降低20％，而增益降低80％。

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