Improved StrongARM latch comparator: Design, analysis and performance evaluation

机译：改进的StrongARM锁存比较器：设计，分析和性能评估

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This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.

机译：本文介绍了一种改进的StrongARM锁存比较器，该器件在90nm和32nm CMOS技术中进行了设计和仿真。与传统设计相比，提出的设计在能源效率方面提高了7％，在速度方面提高了14％，在时钟馈通方面平均降低了41％。新架构还通过减少增强性能所需的必需晶体管来最大程度地减小了面积。

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《Conference on Ph.D. Research in Microelectronics and Electronics》|2017年|89-92|共4页
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Abdullah Almansouri; Abdullah Alturki; Abdullah Alshehri; Talal Al-Attar; Hossein Fariborzi;
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关键词
Transistors; Latches; Clocks; Capacitors; Logic gates; Delays; Capacitance;

机译：晶体管;锁存器;时钟;电容器;逻辑门;延迟;电容;

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专利

1. Characterization and design of GaAs SCFL latched comparators based on improved linearized models [J] . Feng S., Seitzer D. IEEE Transactions on Circuits and Systems. 1 . 1995,第6期

机译：基于改进的线性化模型的GaAs SCFL锁存比较器的表征和设计
2. Characterization and design of GaAs SCFL latched comparators basedon improved linearized models [J] . Feng S., Seitzer D. IEEE Transactions on Circuits and Systems. I, Regular Papers . 1995,第6期

机译：基于改进的线性化模型的GaAs SCFL锁存比较器的表征和设计
3. High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock [J] . LIAN Pengfei, WU Bin, WANG Han, 上海交通大学学报（英文版） . 2019,第003期
4. Improved StrongARM latch comparator: Design, analysis and performance evaluation [C] . Abdullah Almansouri, Abdullah Alturki, Abdullah Alshehri, Conference on Ph.D. Research in Microelectronics and Electronics . 2017

机译：改进的StrongArm Latch比较器：设计，分析和绩效评估
5. Low phase noise oscillator design. A design methodology for improving performance: Theoretical analysis, CAD simulations, and prototype building. [D] . Mansour, Makram Monzer. 2004

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7. Analysis and Design of a 32nm FinFET Dynamic Latch Comparator [O] . Mir Muntasir Hossain, Satyendra N. Biswas 2019

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Improved StrongARM latch comparator: Design, analysis and performance evaluation

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