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首页> 外文会议>IEEE Nanotechnology Materials and Devices Conference >Modeling graphene FET frequency doubler with integrated quantum capacitance effects using quartic equation technique
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Modeling graphene FET frequency doubler with integrated quantum capacitance effects using quartic equation technique

机译：使用四次方程技术建模具有集成量子电容效应的石墨烯FET倍频器

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The need for placing more number of transistors in the core area by shrinking of electronic devices has brought out the necessity of scaling down the Field Effect Transistor (FET) devices. According to the current equation of existing MOSFET device the parameters which can increase the device current is probably channel width and the mobility of electrons and holes. The parameter which can help in improving the device performance will be the mobility of electrons and holes. Hence the necessity of replacing the channel material has become a leading research work in nano electronics. The allotrope of carbon atom - Graphene has the most required mobility range which can help in scaling down the currently available MOSFET devices. Some of the parameters which can be improved due to the replacement of channel material is the device drain current, reduction in the amount of impurity added to obtain the required drain current. A scaled down 15nm Dual Gate Graphene Field Effect Transistor is modeled in this work. As the device is scaled down to a such a narrow range the necessity of investigating the device parameters in a nano scale has been carried out using a novel approach of segmenting the channel. An additional focus in this paper is to employ a computationally efficient method for including the Quantum Capacitance effect. The most common methodology for obtaining the values for quantum capacitance is through solving the equations simultaneously as proposed in [1],[2]. The parameters of interest like quantum capacitance and channel potential are assumed initially and the equations are solved until the assumed parameter value and the obtained value are equal. This not only increases the simulation time but also ends up in approximate result values which are complex. The complex solutions cannot be separated into a real and imaginary value in verilog-a as well as in verilog-ams language as given in [3],[4], to enable circuit compatibility. Moreover the approximate results obtained through the existing methodologies are of huge margin for a 15nm scaled down device. This makes it difficult to implement dual gate GFET in cadence - virtuoso environment. Hence the only way to implement the equations in a circuit level of simulation is to bring out the results as real value and not a complex number. In order to avoid complex solutions the only way is to convert the equations into a polynomial. Hence a novel method which uses a fourth order polynomial known as quartic equation in which the quantum capacitance is derived from the channel potential equation is proposed. The methodology adopted in this work is quartic equation whose results are real valued solutions and hence overcomes the complex number solutions obtained so far. This makes it possible for the model to be developed in verilog-a and incorporated as circuit model. The proposed fourth order polynomial equation can be used to calculate quantum capacitance for any device which obeys the ballistic transport. Hence the device structure proposed in this work is limited to ballistic structure. Ballistic transport of electrons can be obtained when the length and width of the channel is lesser than the mean free path. A N-type impurity of about 2.63×1011cm-2 (calculated, not presented here) is added in order to achieve a mobility of 2497 cm/Vs. Impurities can be further added but it will lead to increased scattering of electrons which will affect the ballistic structure. Hence further addition of impurity to enhance the mobility is stopped. In this model the carriers' Fermi velocity of 106 m/s, tox of 1.5nm (top and bottom), length (L) of 15nm, a width (W) of 150 nm, Cox(bottom gate) of 23.024×10-3 F/m are used and the determined value of mobility is found to be better as reported in Table 1.
机译：由于电子设备的缩小，需要在核心区域中放置更多数量的晶体管，这导致缩小场效应晶体管（FET）器件的必要性。根据现有MOSFET器件的电流方程，可以增加器件电流的参数可能是沟道宽度以及电子和空穴的迁移率。有助于改善器件性能的参数将是电子和空穴的迁移率。因此，更换沟道材料的必要性已经成为纳米电子学中的一项主要研究工作。碳原子的同素异形体-石墨烯具有最需要的迁移率范围，可以帮助缩小当前可用的MOSFET器件的尺寸。由于更换沟道材料而可以改善的一些参数是器件的漏极电流，减少为获得所需漏极电流而添加的杂质数量。在这项工作中对缩小的15nm双栅极石墨烯场效应晶体管进行了建模。由于设备被缩小到如此窄的范围，因此已经使用分割通道的新颖方法进行了以纳米尺度研究设备参数的必要性。本文的另一个重点是采用一种计算有效的方法来包括量子电容效应。获得量子电容值最常用的方法是同时求解方程，如[1]，[2]中所提出的。最初假定感兴趣的参数，例如量子电容和沟道电势，并求解方程，直到假定的参数值和获得的值相等。这不仅增加了仿真时间，而且最终得到了复杂的近似结果值。复杂的解决方案不能用[3]，[4]中给出的verilog-a以及verilog-ams语言分为实数和虚数，以实现电路兼容性。此外，通过现有方法获得的近似结果对于15nm缩小器件具有巨大的优势。这使得很难在节奏-虚拟环境中实现双栅极GFET。因此，在电路仿真水平上实现方程式的唯一方法是将结果显示为真实值，而不是复数。为了避免复杂的解决方案，唯一的方法是将方程式转换为多项式。因此，提出了一种新的方法，该方法使用称为四次方程的四阶多项式，其中从沟道电势方程导出量子电容。这项工作采用的方法是四次方程，其结果是实值解，因此克服了迄今为止获得的复数解。这使得该模型可以在verilog-a中开发并合并为电路模型。所提出的四阶多项式方程可用于计算任何服从弹道传输的设备的量子电容。因此，这项工作中提出的装置结构仅限于弹道结构。当通道的长度和宽度小于平均自由程时，可以获得电子的弹道传输。 N型杂质约为2.63×10 11 厘米 -2 添加（计算，此处未显示）以达到2497 cm / Vs的迁移率。可以进一步添加杂质，但这会导致电子散射增加，从而影响弹道结构。因此，停止了进一步添加杂质以提高迁移率。在此模型中，载流子的费米速度为10 6 使用m / s，1.5nm（顶部和底部）的tox，15nm的长度（L），150nm的宽度（W），23.024×10-3 F / m的Cox（底栅），并确定值如表1所示，发现流动性更好。

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