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Deep neural network accelerator based on FPGA

机译：基于FPGA的深神经网络加速器

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In this work, we propose an efficient architecture for the hardware realization of deep neural networks on reconfigurable computing platforms like FPGA. The proposed neural network architecture employs only one single physical computing layer to perform the whole computational fabric of fully-connected feedforward deep neural networks with customizable number of layers, number of neurons per layer and number of inputs. The inputs, weights and outputs of the network are represented in 16-bit half-precision floating-point number format. The network weights are hard-coded using on-chip memory of FPGA devices, allowing for very fast computation. For performance evaluation, the handwritten digit recognition application with MNIST database is performed, which reported a recognition rate of 97.20% and a peak performance of 15.81 kFPS when using a deep neural network of size 784-40-40-10 on the Xilinx Virtex-5 XC5VLX-110T device. When implementing a deep neural network of size 784-126-126-10 for MNIST database on the Xilinx ZynQ-7000 XC7Z045 device, the recognition rate is 98.16% and the peak performance is 15.90 kFPS.
机译：在这项工作中，我们提出了一种有效的架构，用于在FPGA这样的可重新配置计算平台上的深度神经网络的硬件实现。所提出的神经网络架构只采用一个单个物理计算层，以通过可定制的层数，每层的神经元数和输入数量来执行全连接的前馈深神经网络的整个计算结构。网络的输入，权重和输出以16比特半精度浮点数格式表示。使用FPGA器件的片上存储器进行硬编码网络权重，允许非常快速地计算。对于性能评估，执行具有MNIST数据库的手写数字识别应用，其中报告了在Xilinx Virtex上的大小784-40-40-10的深神经网络中的识别率为97.20 ％和15.81 kFP的峰值性能-5 XC5VLX-110T设备。在Xilinx Zynq-7000 XC7Z045设备上实现Mnist数据库大小784-126-126-10的深神经网络时，识别率为98.16 ％，峰值性能为15.90 kfps。

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