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Speeding-Up Robustness Assessment of HDL Models through Profiling and Multi-Level Fault Injection

机译：通过分析和多级故障注入来加快HDL模型的鲁棒性评估

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Simulation-based fault injection is an indispensable technique to assess the robustness of hardware components defined by means of hardware description languages (HDL). However, the high complexity of modern hardware and its strict verification accuracy requirements lead to an unfeasible number of fault injection experiments, even when following statistical (instead of exhaustive) approaches, as accurate implementation-level models are up to three orders of magnitude slower than (inaccurate) behavioural ones. This paper proposes the combined use of multi-level fault injection in sequential logic and the profiling of the use of combinational logic to guarantee results' accuracy while keeping experimentation duration within reasonable time-bounds. First, the sequential logic generated at the implementation-level model is matched with associated structures at its related behavioural-level model. In such a way, most fault injection experiments targeting sequential logic could be executed at the much faster behavioural level, while maintaining the accuracy of results. Second, by profiling the implementation-level model, run-time statistics (inactive macrocells, switching activity, etc.) can be exploited to keep result precision while reducing the number of experiments targeting combinational logic. The case study of three embedded processor models illustrates both approaches and quantifies the experimental speed-up derived from their combined use.
机译：基于仿真的故障注入是评估借助硬件描述语言（HDL）定义的硬件组件的鲁棒性的必不可少的技术。但是，现代硬件的高度复杂性及其严格的验证精度要求导致无法进行大量的故障注入实验，即使遵循统计（而非穷举）方法，因为准确的实现级别模型的速度比速度慢了三个数量级。 （不准确的）行为行为。本文提出了在顺序逻辑中结合使用多级故障注入，以及在保证实验持续时间在合理时限内的同时，使用组合逻辑来保证结果的准确性。首先，将在实现级别的模型中生成的顺序逻辑与其相关的行为级别的模型中的关联结构进行匹配。这样，大多数针对顺序逻辑的故障注入实验都可以在更快的行为水平上执行，同时保持结果的准确性。其次，通过对实现级别的模型进行概要分析，可以利用运行时统计信息（无效的宏单元，切换活动等）来保持结果的准确性，同时减少针对组合逻辑的实验次数。三种嵌入式处理器模型的案例研究说明了这两种方法，并量化了它们的组合使用所带来的实验性提速。

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