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Transistor-Level Analysis of Dynamic Delay Models

机译:动态延迟模型的晶体管级分析

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Delay estimation is a crucial task in digital circuit design as it provides the possibility to assure the desired functionality, but also prevents undesired behavior very early. For this purpose elaborate delay models like the Degradation Delay Model (DDM) and the Involution Delay Model (IDM) have been proposed in the past, which facilitate accurate dynamic timing analysis: Both use delay functions that determine the delay of the current input transition based on the time difference T to the previous output one. Currently, however, extensive analog simulations are necessary to determine the (parameters of the) delay function, which is a very time-consuming and cumbersome task and thus limits the applicability of these models. In this paper, we therefore thoroughly investigate the characterization procedures of a CMOS inverter on the transistor level in order to derive analytical expressions for the delay functions. Based on reasonably simple transistor models we identify three operation regions, each described by a different estimation function. Using simulations with two independent technologies, we show that our predictions are not only accurate but also reasonably robust w.r.t. variations. Our results furthermore indicate that the exponential fitting proposed for DDM is actually only partially valid, while our analytic approach can be applied on the whole range. Even the more complex IDM is predicted reasonably accurate.
机译:延迟估计是数字电路设计中的关键任务,因为它可以确保所需的功能,而且可以尽早防止不良行为。为此,过去已经提出了复杂的延迟模型,例如退化延迟模型(DDM)和对合延迟模型(IDM),它们有助于精确的动态时序分析:两者都使用确定当前输入转换延迟的延迟函数。时间差T到前一个输出。然而,当前,需要大量的模拟仿真来确定延迟函数(的参数),这是非常耗时且繁琐的任务,因此限制了这些模型的适用性。因此,在本文中,我们将在晶体管级上彻底研究CMOS反相器的表征过程,以便得出延迟函数的解析表达式。基于合理简单的晶体管模型,我们确定了三个工作区域,每个工作区域均由不同的估计函数来描述。通过使用两种独立技术进行的仿真,我们证明了我们的预测不仅准确,而且具有相当强的w.r.t.变化。我们的结果进一步表明,针对DDM提出的指数拟合实际上仅部分有效,而我们的分析方法可以应用于整个范围。甚至更复杂的IDM都被预测为相当准确。

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