A 10-bit High Speed Pipelined ADC

机译：一个10位高速流水线ADC

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The design of a 10-bit, 200MS/s Pipelined Analog to Digital Converter (ADC) is presented in this paper. The implemented pipelined ADC employs techniques such as pipeline stage scaling algorithm, to lower power, capacitor ratio independent conversion scheme, a nested gain boosting technique and thin oxide transistors with clock bootstrapping. The fully realized is measured under different input frequencies with a sampling rate of 200MS/s and it consumes 46.8mW from a 1.8V power supply. The pipelined ADC implemented in 130nm CMOS technology exhibits signal-to-noise plus distortion ration SNDR of 54.7dB and occupies a die area of 0.31mm~2.

机译：本文提出了10位，200ms / s流水线模拟与数字转换器（ADC）的设计。所实现的流水线ADC采用诸如流水线级缩放算法的技术，降低功率，电容器比独立转换方案，具有时钟自动启动的嵌套增益升压技术和薄氧化物晶体管。完全实现的在不同的输入频率下测量，采样率为200ms / s，它从1.8V电源消耗46.8MW。在130nm CMOS技术中实现的流水线ADC具有54.7dB的信号对噪声加失真SNDR，占用0.31mm〜2的模具面积。

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《International Conference on Inventive Systems and Control》|2018年|729-1459p|共6页
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作者
Alfakhri M. Murshed; K. Lokesh Krishna; M. Abdullah Saif; K. Anuradha;
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中图分类 TP2-53;
关键词
low power; data converter; op-amp; time-interleaving; high linearity; comparator; and amplifier;

机译：低功率;数据转换器;OP-AMP;时间交织;高线性;比较器;和放大器;

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专利

1. A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique [J] . Sam D. S. Shylu, Paul P. Sam Circuit World . 2021,第3期

机译：具有并行采样和交换OP-AMP共享技术的10位200 MS / S流水线ADC
2. A low-power 10-bit CCP-based pipelined ADC using a multilevel variable current source MDAC and an ultra-low-power double-tail dynamic latch [J] . Firouzkouhi Hossein, Ashraf Mohammadreza International journal of circuit theory and applications . 2021,第3期

机译：基于低功耗10位CCP的流水线ADC，使用多级可变电流源MDAC和超低功耗双尾动态闩锁
3. A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS [J] . Kyoung-Jun Moon, Dong-Shin Jo, Wan Kim, IEEE Journal of Solid-State Circuits . 2019,第9期

机译：9.1-ENOB 6mW 10位500-MS / s流水线SAR ADC，具有在28nm CMOS中进行电流模式残留处理的功能
4. A 10-bit high speed pipelined ADC [C] . Alfakhri M. Murshed, K. Lokesh Krishna, M. Abdullah Saif, 2018 2nd International Conference on Inventive Systems and Control . 2018

机译：10位高速流水线ADC
5. A low-voltage low-power 10-bit pipeline ADC in 90nm digital CMOS technology. [D] . Wang, Robert. 2004

机译：采用90nm数字CMOS技术的低压低功耗10位管线ADC。
6. A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices [O] . Yongkui Yang, Jun Zhou, Xin Liu, 2018

机译：适用于无线植入式医疗设备的10位300 kS / s无参考电压稳压器SAR ADC
7. A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS [O] . Shafti Ali, Yavari Mohammad 2014

机译：基于过零的10位100 MS / s流水线ADC，电流受控于90 nm CMOS

A 10-bit High Speed Pipelined ADC

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