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首页> 外文会议>International Conference on Inventive Systems and Control >Design Topologies For Low Power Cmos Full Adder
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Design Topologies For Low Power Cmos Full Adder

机译：低功耗CMOS完整加法器的设计拓扑

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The main building blocks used in digital signal processing and multimedia applications are the adders and multipliers. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this we present different topologies of full adder by using CMOS technology. Performance comparison of the six different cmos full adder structures are presented in this paper those full adders are Serf full adder,16T full adder, 14T full adder, TG-cmos full adder, static cmos full adder and TFA full adder. All these full adder structures are developed by using S-edit and T-spice of Tanner EDA tools. And the results shows that SERF full adder is constructed by using less transistor count as less as 10 transistor and also consuming less power.
机译：数字信号处理和多媒体应用中使用的主构件块是加法器和乘法器。更好的加法结构性能更好将是总方面的乘数的性能。降低电路电平的功耗，延迟和区域被认为是开发低功率系统的主要因素之一。在此，我们通过使用CMOS技术呈现完整加法器的不同拓扑。本文提出了六种不同CMOS完整加法器结构的性能比较，这些完整的加法器是SERF全加法器，16T全加法器，14T全加法器，TG-CMOS全加法器，静态CMOS全加法器和TFA全加法器。所有这些完整的加法器结构都是通过使用Tanner EDA工具的S-Edit和T-Spice开发的。结果表明，SERF全加法器通过使用较少的晶体管计数为10晶体管构造，并且也消耗更少的功率。

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