The paper presents the FPGA implementation of a programmable asynchronous digital circuit (henceforth called AE-map) that remaps 'address events'. Address event representation (AER) is an event driven communication protocol originally used in VLSI implementations of neural networks to transfer action potentials (neural voltage pulses) between neurons. More generally speaking it is suited to transmit a number of analog values that are coded in frequency of events over an asynchronous digital bus. The AE-map allows one to redirect such events between an AE sender and an AE receiver, thereby for instance programming the connection scheme of a neural network. Earlier approaches for redirecting AEs have used digital synchronous devices such as DSPs or microcontrollers. The simpler and more dedicated asynchronous solution presented here is more energy efficient, does not impose a discretization on the time axis and achieves a much faster throughput. In the present implementation AEs (9 bit input, 7 bit output) can be processed at intervals of less than 84 ns per output AE.
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