Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

机译：用于将保护环放置在芯片布局中的自动方法，以防止CMOS IC的闩锁

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A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS ICs. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS ICs. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "guard ring automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.

机译：提出了一种程序方法来自动将保护环放置在芯片布局中，以提高CMOS IC的闩锁抗扰性。 I / O单元与内部电路之间的附加保护环已得到实践证明，可以显着提高CMOS IC的闩锁抗扰性。因此，可以将从I / O单元到内部电路的布局间距减小到合理的距离，以节省总芯片尺寸。在本文中，提出了一种“防护环自动化”程序，以在布局中实现附加的防护环，以使布局更自动，更准确。

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《Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on》|2001年|P.113-116|共4页
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Ming-Dou Ker; Hsin-Chin Jiang; Jeng-Jie Peng;
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中图分类无线电电子学、电信技术;
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1. Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology [J] . Ming-Dou Ker, Wen-Yu Lo IEEE Transactions on Semiconductor Manufacturing . 2003,第2期

机译：提取紧凑布局规则以防止深亚微米体CMOS技术中的闩锁的方法
2. Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology [J] . Ming-Dou Ker, Wen-Yu Lo IEEE Transactions on Semiconductor Manufacturing . 2003,第2期

机译：提取紧凑布局规则以防止深亚微米体CMOS技术中的闩锁的方法
3. Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology [J] . Ming-Dou Ker, Wen-Yu Lo IEEE Transactions on Semiconductor Manufacturing . 2003,第2期

机译：深度亚微米批量CMOS技术提取紧凑布局规则的方法论
4. Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS ICs [C] . Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, IEEE International Conference on Electronics, Circuits and Systems . 2001

机译：将警卫响铃放入芯片布局的自动方法，以防止CMOS IC中的闩锁
5. Transistor placement algorithm for automatic layout synthesis of CMOS/BiCMOS logic and interface circuits. [D] . Xia, Hongxia. 1994

机译：晶体管放置算法，用于CMOS / BiCMOS逻辑和接口电路的自动布局合成。
6. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking [O] . Ashfaque Uddin, Kaveh Milaninia, Chin-Hsuan Chen, -1

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7. Methodology for Placing Localized Guard Rings to Reduce Substrate Noise in Mixed-Signal Circuits [O] . Emre Salman, Eby G. Friedman 2012

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8. Correlation of Picosecond Laser-Induced Latchup and Energetic Particle- Induced Latchup in CMOS Test Structures [R] . Moss, S. C. , Lalumondiere, S. D. , Scarpulla, J. R. , 2000

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Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

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