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SEMICONDUCTOR DEVICE AND GUARD RING LAYOUT METHOD TO OPTIMIZE LATCH-UP PREVENTING EFFECT
SEMICONDUCTOR DEVICE AND GUARD RING LAYOUT METHOD TO OPTIMIZE LATCH-UP PREVENTING EFFECT
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机译：半导体器件和保护环布局方法，可优化闩锁预防效果
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摘要
PROBLEM TO BE SOLVED: To provide a semiconductor device as well as its layout method where the performance (amplification factor) of a parasitic element is halved than before by optimizing the layout method for a guard ring.;SOLUTION: The activation/deactivation of a parasitic element is intentionally controlled by 'concentrating', 'excluding', 'selecting' VSS substrate contact. Since the parasitic element is activated at a part where the VSS substrate contact is 'concentrated', an excessive current is sucked up by inserting an epi-contract/well-contact into the part. The substrate contact is 'excluded' as possible in a circuit region where the parasitic element is wanted to be deactivated. These regions are intentionally 'selected' on an actual chip. By multiplexing a guard ring, the effect will be two to three times.;COPYRIGHT: (C)2002,JPO
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