In this paper, we consider verification of combinational circuits by test vector simulations. The simulation-based verification under the presence of a fault model uses test pattern generation approach. We show that the test vector generation can be enhanced by techniques used in formal verifications: satisfiability (SAT)- and BDD-based solutions can be combined with the vector simulations. Our method can pass useful information between these disparate approaches. Trade-offs between the three schemes are explored.
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