This paper shows the implementation of the one dimensional discrete cosine transform (1D-DCT) based on the residue number system (RNS). The 1D-DCT has been derived by,the application of a previously developed scaled fast cosine transform (FCT) algorithm that requires a reduced number of multiplications. The processor has been modeled at structural level using VHDL and implemented in Altera FLEX10K devices. This paper shows that the RNS-enabled ID-DCT provides a throughput improvement over the equivalent binary system of up to 62% when 8-bit moduli are used. This is achieved due to the synergy between RNS and modern field programmable logic (FPL) device families.
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