During the RTL design, some Satisfiability Don't Cares (SDCs) of a node can be easily identified and specified by designers. Although, in theory, a synthesis tool can extract all SDCs during gate level minimization, the tool may take a lot of effort or be impossible to obtain all SDCs. In addition, some SDCs of a node may not be (directly) useful for minimizing the node but may become useful after some logic transformation on the node. In this paper our first contribution is to describe a method to efficiently utilize those pre-specified SDCs. Several formulae are proposed to describe the "new" SDCs after some logic transformations. We also provide an efficient framework to apply these transformed SDCs for optimization. Based on the experimental results for benchmark circuits, we show that the presented methodologies are very encouraging.
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