Highly automated FPGA synthesis of application-specific protocol processors

机译：专用协议处理器的高度自动化的FPGA综合

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We present a methodology for synthesizing TTA protocol processors onto CMOS and FPGA from application specifications with reduced designer intervention and a short turn-around time. The methodology builds up on our earlier work in generating synthesizable processor models from system level specifications for 0.18 /spl mu/m CMOS technology. We test the application level methodology by comparing results obtained from a generated FPGA synthesis model to results obtained from a generated CMOS synthesis model. We synthesized an architecture for processing the IPv6 protocol, which resulted in an implementation that achieved the clock speed of 45 MHz. Due to the scalable parallelism of TTA architectures, this corresponds to an approximate throughput of 500 Mbps for IPv6 routing. From the results we were able to conclude that the critical delay in our generated FPGA implementations is formed inside our protocol processing functional units.

机译：我们提供了一种从应用规范中将TTA协议处理器合成到CMOS和FPGA上的方法，从而减少了设计人员的干预并缩短了周转时间。该方法基于我们先前的工作，该工作是根据系统级规范为0.18 / spl mu / m CMOS技术生成可综合处理器模型的。通过比较从生成的FPGA合成模型获得的结果与从生成的CMOS合成模型获得的结果，我们测试了应用程序级方法。我们综合了用于处理IPv6协议的体系结构，从而实现了实现45 MHz时钟速度的实现。由于TTA架构具有可扩展的并行性，因此这对应于IPv6路由的大约500 Mbps的吞吐量。从结果中我们可以得出结论，我们生成的FPGA实现中的关键延迟是在协议处理功能单元内部形成的。

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《Field Programmable Logic and Applications, 2005. International Conference on》|2005年|P.269-274|共6页
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Virtanen S.; Truscan D.; Paakkulainen J.; Isoaho J.; Lilius J.;
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中图分类工业技术;
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CMOS digital integrated circuits; application specific integrated circuits; circuit CAD; field programmable gate arrays; integrated circuit design; integrated circuit modelling; microprocessor chips; parallel architectures; routing protocols; 0.18 micron; 45 MHz; C;

机译：CMOS数字集成电路;专用集成电路;电路CAD;现场可编程门阵列;集成电路设计;集成电路建模;微处理器芯片;并行架构;路由协议; 0.18微米; 45 MHz; C;

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Highly automated FPGA synthesis of application-specific protocol processors

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