It is seen that power dissipation during test mode is quite high compared to that during the functional mode of operation of a digital circuit. This may lead to damage of certain chips only because they are tested, leading to unnecessary loss of yield. This paper presents a simple yet efficient low power scheme for scan-based BIST. It reduces test length and switching-activity in CUTs reducing power dissipation during test mode without compromising fault coverage. Experiments conducted on ISCAS89 benchmark circuits demonstrate that proposed scheme gives better fault coverage with a large reduction in transitions reducing power dissipation during testing.
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