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首页> 外文期刊>Journal of Low Power Electronics >Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip
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Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip

机译：使用测试元件组芯片的低功耗Logic-BIST方案的物理功耗评估

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摘要

High power dissipation in scan-based Logic-BIST testing is a vital issue. Low power approaches to handle all power problems of Logic-BIST have been proposed in our prior works, in which the toggle rate (switching activity) during the test operation (scan and capture) is well controlled. While significant reduction of the toggle rate has been confirmed, the amount of power reduction on a real chip is not known yet. In this paper, we implement the low power approaches on a Test Element Group (TEG) chip to investigate the physical effects of the low power scheme on a real chip in terms of current dissipation, voltage-drop and delay variations. Experimental results confirm the effectiveness of the low power scheme and show strong correlation between the simulated toggle rate and the measured (current, voltage-drop and delay variation) values. They show that the simulated toggle rate can be used as a good indicator of test power in test generation or design. The measured results of the actual power reduction caused by the toggle rate reduction should be valuable references to the low power test design.
机译：在基于扫描的Logic-BIST测试中，高功耗是至关重要的问题。在我们以前的工作中已经提出了解决Logic-BIST的所有功耗问题的低功耗方法，其中可以很好地控制测试操作（扫描和捕获）过程中的触发速率（开关活动）。虽然已经确认了开关速率的显着降低，但尚不知道实际芯片上的功率降低量。在本文中，我们在测试元件组（TEG）芯片上实现了低功耗方法，以从电流耗散，压降和延迟变化方面研究低功耗方案对实际芯片的物理影响。实验结果证实了低功耗方案的有效性，并显示了模拟的触发速率与测得的（电流，电压降和延迟变化）值之间的强相关性。他们表明，模拟的触发速率可以用作测试生成或设计中测试功率的良好指标。由触发速率降低引起的实际功率降低的测量结果应该是低功耗测试设计的宝贵参考。

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