首页> 外文会议>The 2008 International Conference on Embedded Software and Systems Symposia(ICESS 2008)(2008国际嵌入式系统及嵌入式软件会议)论文集 >A simulator for multi-core processor micro-architecture featuring inter-core communication, power and thermal behavior
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A simulator for multi-core processor micro-architecture featuring inter-core communication, power and thermal behavior

机译:一种用于多核处理器微体系结构的模拟器,具有内核间通信,功率和热行为

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To effectively evaluate thermal behavior and inter-core communication on multi-core processors,we propose a simulation methodology and the corresponding implementation with runtime power and temperature calculation in this paper. The multi-core simulator is extended from our previous work,i.e. a heteromerous dual-core simulator. In our updated simulator,the well-established power model Wattch and a transient thermal simulation algorithm TILTS are integrated. The simulator is able to provide the runtime power and temperature metrics with little additional overhead compared with the original performance simulator. These results are illustrated with multimedia applications making use of all cores via inter-core communications.As far as we learn,we would like to highlight that our simulator is the first multi-core processor simulator based on SimpleScalar with thermal behavior and inter-core communication enabled. This simulator must be helpful for processor architects to make early decisions on thermal and performance trade-offs.
机译:为了有效地评估多核处理器上的热行为和内核间通信,我们提出了一种仿真方法和相应的实现,并带有运行时功率和温度计算。多核模拟器是我们先前工作的扩展,即异构双核模拟器。在我们更新的仿真器中,将完善的功率模型Wattch和瞬态热仿真算法TILTS集成在一起。与原始性能模拟器相比,该模拟器能够以很少的额外开销提供运行时功率和温度指标。这些结果在通过内核间通信利用所有内核的多媒体应用程序中得到了说明。据我们了解,我们要强调的是,我们的模拟器是第一个基于SimpleScalar的具有热行为和内核间性能的多核处理器模拟器。通讯已启用。该模拟器必须有助于处理器架构师就热和性能的折衷做出早期决策。

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