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Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel

机译：无植入SiGe量子阱pFET：一种新颖的，高度可扩展的，低热预算的器件，具有提高的源/漏和高迁移率通道

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A novel bulk-Si based pMOSFET structure is presented featuring a high-mobility SiGe0.45 channel and raised SiGe0.25 source/drains. This device offers enhanced scalability with respect to standard pMOS devices, leading to 50% improved drive current. 30nm gate length devices show a high drive current of ∼580 µA/µm for IOFF=100nA/µm, DIBL=126mV/V, SS=80mV/dec, showing superior electro- statics without halo implants. Finally, the compatibility with additional strain-boosters is demonstrated.

机译：提出了一种新颖的Bulk-Si基于PMOSFET结构，采用高迁移性SiGe 0.45 通道，并凸起SiGe 0.25 源/排水管。该设备对标准PMOS设备提供了增强的可扩展性，导致50％改进的驱动电流。 30nm栅极长度器件显示为I = 100na /μm，dibl = 126mV / v，ss = 80mV / DEC的高驱动电流，显示出卓越的电静音。最后，证明了与额外的应变助力器的兼容性。

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《2010 IEEE International Electron Devices Meeting》|2010年|p.1-4|共4页
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1. High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension [J] . Khakifirooz A.Cheng K.Cai J.Kimball A.Kulkarni P.Reznicek A.Adam T.Edge L.Bu H.Doris B.Shahidi G. Electron Device Letters, IEEE . 2011,第3期

机译：具有原位掺杂SiGe的高性能部分耗尽SOI PFET提高了源极/漏极和无植入扩展
2. Scalability comparison between raised- and embedded-SiGe source/drain structures for Sio.55Geo.45 implant free quantum well pFET [J] . Yamaguchi S., Witters L., Mitard J., Microelectronics & Reliability . 2018,第APRa期

机译：Sio.55Geo.45无植入量子阱pFET的凸起和嵌入式SiGe源/漏结构之间的可扩展性比较
3. Experimental demonstration for ultra-low on-resistance in raised source/drain In_(0.53)Ga_(0.47)As QW-MOSFETs with implant-free process [J] . Liao M.-H., Chan P.-G. Journal of Physics, D. Applied Physics: A Europhysics Journal . 2013,第39期

机译：采用无注入工艺的高源/漏In_（0.53）Ga_（0.47）As QW-MOSFET超低导通电阻的实验演示
4. Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel [C] . (missing) IEEE International Electron Devices Meeting . 2010

机译：无植入式SiGe量子井PFET：一种新型，高度可扩展和低热预算装置，具有凸出的源/漏极和高移动通道
5. Design, fabrication, and characterization of shallow trench isolation and raised source/drains for 100nm CMOS. [D] . VanDerVoorn, Peter Jon. 1998

机译：用于100nm CMOS的浅沟槽隔离和凸起的源极/漏极的设计，制造和表征。
6. Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors [O] . Guilei Wang, Jun Luo, Changliang Qin, 2017

机译：用于22nm体PMOS晶体管的HK和MG集成了源极和漏极中的高应变SiGe
7. High Performance pMOSFETs with High Ge Fraction Strained SiGe-heterostructure-channel and Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD [O] . Shinobu Takehiro, Masao Sakuraba, Junichi Murota, 2006

机译：具有高GE分数的高性能PMOSFET应变SiGE-异质结构 - 通过选择性B掺杂SiGE CVD形成的超肺源/漏极

Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel

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