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Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware

机译:通过可扩展的Spiking ConvNet硬件进行新皮质无框视觉感测和处理

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This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern and object recognition tasks operating at mili second delay throughputs. Although such hardware would require hundreds of individual convolutional modules and thus is presently not yet available, we discuss methods and technologies for implementing it in the near future. On the other hand, we provide precise behavioral simulations of large scale spiking AER convolutional hardware and evaluate its performance, by using performance figures of already available AER convolution chips fed with real sensory data obtained from physically available AER motion retina chips. We provide simulation results of systems trained for people recognition, showing recognition delays of a few miliseconds from stimulus onset. ConvNets show good up scaling behavior and possibilities for being implemented efficiently with new nano scale hybrid CMOSonCMOS technologies.
机译:本文总结了如何使用Spiking神经网络地址事件表示(AER)技术在硬件中实现卷积神经网络(ConvNets),以实现以毫秒级延迟吞吐量运行的复杂模式和对象识别任务。尽管这样的硬件将需要数百个单独的卷积模块,因此目前尚不可用,但我们讨论了在不久的将来实现它的方法和技术。另一方面,我们通过使用已经提供的AER卷积芯片的性能数据,并从物理上可用的AER运动视网膜芯片获得的真实感官数据,提供大规模加标AER卷积硬件的精确行为模拟,并评估其性能。我们提供经过训练的可识别人的系统的仿真结果,显示从刺激发生几毫秒后的识别延迟。 ConvNets表现出良好的向上缩放行为,并具有通过新型纳米级混合CMOS / nonCMOS技术有效实施的可能性。

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