CDM effect on a 65nm SOC LNA

机译：CDM对65nm SOC LNA的影响

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An investigation was performed into the cause of unexpectedly low CDM performance of a 65nm SOC LNA. The main culprit was found to be STI diode overshoot due to the fast CDM current rise time. Solutions included replacing the STI diodes with gated diodes and with incorporating a new type of secondary clamp.

机译：对65nm SOC LNA的CDM性能异常低的原因进行了调查。罪魁祸首是由于快速的CDM电流上升时间而导致的STI二极管过冲。解决方案包括将STI二极管替换为门控二极管，并合并一种新型的次级钳位器。

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《2010 32nd Electrical Overstress/ Electrostatic Discharge Symposium》|2010年|1-8|共8页
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Worley Eugene R.; Jalilizeinali Reza; Dundigal Sreeker; Siansuri Evan; Chang Tony; Mohan Vivek; Zhang Xiaonan;
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中图分类电器;
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2. Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation [J] . Jie Li, Xing Wan, Jianbing Wu, Chinese Journal of Electronics . 2017,第1期

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3. Cache Power Optimization Based on Compare-Based Adaptive Clock Gating and Its 65nm SoC Implementation [J] . LI Jie, WAN Xing, WU Jianbing, 电子学报（英文版） . 2017,第001期

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4. CDM effect on a 65nm SOC LNA [C] . Worley Eugene R., Jalilizeinali Reza, Dundigal Sreeker, 2010 32nd Electrical Overstress/ Electrostatic Discharge Symposium . 2010

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CDM effect on a 65nm SOC LNA

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