The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array comparison has been experimentally validated in order to take into account both gate coupling and avalanche current effects. Using TLP and electrical test methods, two orders of magnitude improvement of SPC has been demonstrated by implementation changes to array design. The effects of the Pbody shading and the drain region design have been quantified and analyzed by numerical simulation, and their physical nature has been discussed.
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机译：对于在BCD工艺中集成100 V NLDMOS阵列的情况，已经研究了ESD模式下集成电源阵列的自保护能力（SPC）。为了兼顾栅极耦合和雪崩电流效应，已经通过实验验证了一种新的实用的阵列比较方法。使用TLP和电气测试方法，通过更改阵列设计实现了SPC的两个数量级的改进。通过数值模拟对Pbody阴影和漏极区域设计的影响进行了量化和分析，并讨论了它们的物理性质。
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