首页> 外文会议>2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers >A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance
【24h】

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance

机译:0.5至2.5Gb / s的无参考半速率数字CDR,具有无限的频率采集范围,并改善了输入占空比误差容限

获取原文

摘要

Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.
机译:具有宽频率采集范围的时钟和数据恢复(CDR)电路为光通信网络提供了灵活性,通过基于活动的速率自适应来帮助降低链路功率,并通过单芯片多标准解决方案将成本降至最低。从传入的随机数据流中提取比特率是实现无参考CDR的主要挑战。常规的旋转频率检测器的采集范围有限,约为VCO频率的±50%,消耗的功率大,并且易于谐波锁定。扩展其范围需要额外的高速电路和复杂的状态机[1]。 [2]中基于DLL的体系结构要求将高速数据通过耗电的缓冲区的长字符串传递,提出了严格的匹配要求,并且仅适用于环形振荡器。其他方法需要详细的统计[3]或时序分析[4]。此外,所有上述技术仅适用于全速率CDR。在本文中,我们提出了一种无参考的半速率CDR,它使用亚谐波提取方法来实现无限的频率采集范围。该技术能够将CDR锁定在数据任何子速率的40ppm以内(使其适用于任何子速率CDR体系结构),同时不受不良谐波锁定的影响。该CDR还集成了一个校准环路,以提高对输入占空比误差的鲁棒性。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号